<h3>Minimum qualifications:</h3> <ul> <li>Bachelor's degree in Computer Science, Electrical Engineering, a related field, or equivalent practical experience.<br> </li> <li>Experience with SystemVerilog (e.g. SystemVerilog Assertions or functional coverage).<br> </li> </ul> <br><h3>Preferred qualifications:</h3> <ul> <li>Master's degree or PhD in Electrical Engineering.<br> </li> <li>Experience with Universal Verification Methodology (UVM).<br> </li> <li>Experienced with the full verification life cycle.<br> </li> </ul>

Software Engineering

(Other)

Design

Sunnyvale, CA, USA

A problem isn't truly solved until it's solved for all. Googlers build products that help create opportunities for everyone, whether down the street or across the globe. Bring your insight, imagination and a healthy disregard for the impossible. Bring everything that makes you unique. Together, we can build for everyone.

United States

Google

ASIC Design Verification Engineer, Machine Learning

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ASIC Design Verification Engineer, Machine Learning

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