<h3>Minimum qualifications:</h3> <ul> <li>Bachelor's degree in Electrical Engineering, Computer Science, or equivalent practical experience.<br> </li> <li>8 years of experience with low power verification and flows.<br> </li> <li>Experience verifying digital logic at the Register Transfer Level (RTL) using SystemVerilog at subsystem or full-chip level.<br> </li> <li>Experience in C/C++ or SystemVerilog based tests and test sequence development.<br> </li> </ul> <br><h3>Preferred qualifications:</h3> <ul> <li>Master's degree in Electrical Engineering or Computer Science.<br> </li> <li>Experience with low power coverage closure and power aware simulations.<br> </li> <li>Experience with debugging power aware simulations issues during bring-up and verification cycle.<br> </li> <li>Knowledge of UPF from the user perspective and low power design strategies and power managers in subsystem or full-chip.<br> </li> </ul>

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Bengaluru, Karnataka, India

Karnataka, India

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Low Power Design Verification Engineer, Silicon

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Low Power Design Verification Engineer, Silicon

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