ASIC Prototyping Hardware Architect

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
  
• 5 years of experience with multimedia architecture and silicon design concepts.
  

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering or Computer Science, with an emphasis on computer architecture.
  
• Experience architecting and designing low power SoC hardware IP in the following areas: Camera ISP, video codecs, display, computer cores, and machine learning accelerators.
  
• Experience in micro architecture, power and performance optimization.
  
• Experience collaborating cross-functionally with system and hardware architecture, IP design and verification, multi-media and ML algorithm, and software development teams.
  
• Experience in micro-architecture design, with the ability to work independently for RTL design prototyping.
• Knowledge of interconnect/fabric, security, multi-level caching architectures, and hardware and digital logic design.
  

About the job

As a member of the CoreIP Hardware Architecture team, you will contribute your RTL development expertise in architecting and prototyping next-generation hardware solutions for camera ISP, video, display, security, and compute core IPs. In this role, you will collaborate closely with system algorithm and hardware architecture teams by providing hardware micro-architecture solutions according to the architecture specifications/requirements. You will develop a new RTL implementation in System Verilog RTL implementation and conduct detailed power and performance analysis for architecture tradeoff evaluations. You'll provide the architecture specifications used by the hardware IP design teams to implement the solutions within the SoC.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

The US base salary range for this full-time position is $150,000-$223,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target for new hire salaries for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google.

Responsibilities

• Develop System Verilog RTL to implement logic for ASIC/SoC products according to next-generation architecture specifications.
  
• Perform digital design verification of complex digital design blocks, and interact with architects to identify important verification scenarios.
  
• Perform detailed data analysis and tradeoff evaluations to improve our hardware architecture solutions.
  
• Define and deliver the hardware IP architecture specifications that meet competitive power, performance, area and image quality targets, which will require owning the targets through to tape-out and product launch.
  
• Collaborate with SoC and System/Experience architects on meeting power, performance and area requirements at the SoC level for multimedia use cases and experiences.