Senior System Integration/Architecture Engineer, TPU, Google Cloud

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
  
• 8 years of experience in architecture, hardware, digital design, and software co-design.
  
• 5 years of experience in Verilog/SystemVerilog.
  
• Experience in two of the following areas: computer architecture, digital design, IP integration (e.g., DDR, PCIe).
  

Preferred qualifications:

• Masters degree in Electrical Engineering, Computer Science, or a related field.
  
• 8 years of experience working in Field-Programmable Gate Array (FPGA) platforms or emulation platforms with IPs such as PCIe, DDR memory, Gigabit Ethernet, Flash.
  
• Experience developing architectures for Machine Learning accelerators.
  
• Experience writing/debugging verilog/RTL code for ASIC/FPGA designs.
  
• Knowledge of chip design flows.
  
• Excellent waveform debug skills.
  

About the job

In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.

In this role, you will integrate complex hardware and software stacks and operate them on emulation platforms for pre-silicon validation of our Cloud TPU projects. You will create software-based custom test cases, workloads, test generators, infrastructure, analysis tools, and debugging tools. In later phases, you will be responsible for silicon bringup, validation, characterization and qualification, and sustaining programs and their quality. You will help ensure our fleet runs at maximum efficiency, and when problems do arise help debug and root cause those issues. You will collaborate with Product Firmware, System Software, ASIC Design and Design verification Engineers in the development of tools, validation firmware, functional and performance tests and testing infrastructure for our platforms and Cloud data center systems.

Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.

Responsibilities

• Bringup chip features through Firmware and driver stack. Integrate and validate complex hardware and software designs in pre-silicon.
• Architect and Design ASIC models for Emulation/FPGA prototypes. Design Register Transfer Level (RTL) transformations to optimize mapping to Emulation/FPGA platforms and design innovative solutions to improve IP modeling.
• Design solutions to improve hardware modeling accuracy and scale to various system configurations and enable serving of ASIC models for software and validation teams.
• Bringup chip features/subsystems on software reference models and hardware prototypes (e.g., Emulation/FPGA) and drive debug discussions with Design/Design Validation/Physical Design/Software/Architecture teams and help root-cause failures.
• Develop the integration plan with software and system partners, coordinate hardware and software delivery and benchmark performance.