CPU RTL Design Manager, Silicon
CPU RTL Design Manager, Silicon
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In-office locations: Mountain View, CA, USA; Austin, TX, USA; Poughkeepsie, NY, USA.
Remote location(s): Oregon, USA.
Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- 10 years of experience in high-performance CPU or AI accelerator logic/RTL design including micro-architecture definition and PPA optimizations.
- 6 years of experience in people management, developing employees.
- Experience with HDL language and front-end design methodology.
- Experience with CPU or AI accelerator integration with SoC.
Preferred qualifications:
- Master's degree or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
- Experience leading front-end design for modern processor components or AI accelerators.
- Experience with ARM Instruction Set Architecture.
- Experience with SoC design, architect, and integration.
About the job
In this role, you will contribute to all phases of designs of
Central Processing Unit (CPU) subsystems from design specification to productization, including integration into goal System on a chips (SoC).
Google's mission is to organize the world's information and make it universally accessible and useful. Our Devices & Services team combines the best of Google AI, Software, and Hardware to create radically helpful experiences for users. We research, design, and develop new technologies and hardware to make our user's interaction with computing faster, seamless, and more powerful. Whether finding new ways to capture and sense the world around us, advancing form factors, or improving interaction methods, the Devices & Services team is making people's lives better through technology.
The US base salary range for this full-time position is $221,000-$314,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target salaries for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.
Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google.
Responsibilities
- Develop CPU subsystem front-end designs, emphasizing micro-architecture and RTL design for the next generation CPU.
- Propose performance enhancing micro-architecture features, and work with Software, Architect, and Performance teams for trade-off studies.
- Deliver designs meeting Performance, Power, Area (PPA) goals with production quality and become familiar with modern techniques, interpret the techniques into design constructs, and languages in order to provide guidance to and participate in the performance evaluation effort.
- Work with the Verification team to ensure production of quality designs, and the physical design and power teams to meet frequency, power, and area goals.
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Google is a global company and, in order to facilitate efficient collaboration and communication globally, English proficiency is a requirement for all roles unless stated otherwise in the job posting.
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