Hardware Architecture Modeling Engineer, TPU

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
  
• 3 years of experience in computer architecture performance analysis, or a PhD degree in lieu of industry experience.
  
• Experience in developing software systems in C++.
  

Preferred qualifications:

• Experience in applying computer architecture principles to solve open-ended problems.
  
• Experience in analyzing workload performance and creating benchmarks.
  
• Experience in hardware and software co-design.
  
• Experience developing in Python.
  
• Knowledge of design of digital logic at the Register Transfer Level (RTL) using Verilog.
  
• Knowledge of processor design or accelerator designs and mapping Machine Learning (ML) models to hardware architectures.
  

About the job

In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.

As the Hardware Architecture Modeling Engineer, you will work with hardware and software architects to model, analyze, and define next-generation TPUs.

Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.

The US base salary range for this full-time position is $127,000-$187,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target salaries for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

Responsibilities

• Work on Machine Learning (ML) workload characterization and benchmarking.
  
• Conduct performance and power analyses and quantitatively evaluate proposals.
  
• Develop architectural and microarchitectural models to enable quantitative analysis.
  
• Collaborate with partners in hardware design, software, compiler, Machine Learning (ML) model and research teams for effective hardware/software codesign.
  
• Propose capabilities and next-generation TPUs and chip roadmap.