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Physical Design CPU Lead, Google Cloud

Google

Google

Design
Tel Aviv-Yafo, Israel
Posted on Dec 20, 2024

Physical Design CPU Lead, Google Cloud

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GoogleTel Aviv, Israel; Haifa, Israel
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Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Tel Aviv, Israel; Haifa, Israel.

Minimum qualifications:

  • Bachelor’s degree in Electrical Engineering or equivalent practical experience.
  • Experience with System on a Chip (SoC) cycles.
  • Experience with advanced design, including clock/voltage domain crossing, DFT, and low power designs.
  • Experience in high-performance, high-frequency, and low-power designs.

Preferred qualifications:

  • Experience in Very Large Scale Integration (VLSI) design in SoC or with multiple-cycles of SoC in ASIC design.
  • Experience coding with System Verilog and scripting with Transaction Control Language (TCL).
  • Experience with layout verification and design rules.

About the job

Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.

Responsibilities

  • Lead physical design of the CPU to tape-out while working with multiple team members.
  • Evaluate and develop physical design methodologies and decide on the System on a Chip (SoC) flow.
  • Work with architects and logic designers to drive architectural feasibility studies, develop timing, power and area design targets, and explore Register-Transfer Level (RTL)/design tradeoffs for physical design closure.
  • Participate in design reviews and track issue resolution, and engage in technical and schedule tradeoff discussions. Create execution plans for projects and manage team efforts from concept to working silicon in volume.
  • Understand architecture and design specifications with the team, and define physical design strategies and tactics to meet quality and schedule goals.

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Google is proud to be an equal opportunity and affirmative action employer. We are committed to building a workforce that is representative of the users we serve, creating a culture of belonging, and providing an equal employment opportunity regardless of race, creed, color, religion, gender, sexual orientation, gender identity/expression, national origin, disability, age, genetic information, veteran status, marital status, pregnancy or related condition (including breastfeeding), expecting or parents-to-be, criminal histories consistent with legal requirements, or any other basis protected by law. See also Google's EEO Policy, Know your rights: workplace discrimination is illegal, Belonging at Google, and How we hire.

If you have a need that requires accommodation, please let us know by completing our Accommodations for Applicants form.

Google is a global company and, in order to facilitate efficient collaboration and communication globally, English proficiency is a requirement for all roles unless stated otherwise in the job posting.

To all recruitment agencies: Google does not accept agency resumes. Please do not forward resumes to our jobs alias, Google employees, or any other organization location. Google is not responsible for any fees related to unsolicited resumes.