Silicon Test Engineer, SoC, Platforms

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or in a related field, or equivalent practical experience.
• 5 years of experience in test engineering or product engineering.
• Experience in Application-Specific Integrated Circuit (ASIC) or SoC DFT test development, bring-up, or debug for NPI prototypes or High Volume Manufacturing.

Preferred qualifications:

• Master's degree in Computer Science, Electrical Engineering, or in a related technical field.
• 10 years of experience in test engineering or product engineering.
• Experience with Automatic Test Equipment (ATE) platforms such as Advantest V93K or Teradyne UltraFlex.
• Experience with Scan/ATPG test development, especially with Streaming Scan Network (SSN)/Streaming Fabric techniques, or Memory BIST test development and repair scheme implementation, including BISR/BIRA.
• Experience Testing Internet Protocols (IP) such as Phase-locked Loops (PLL), Production Verification Testing (PVT) sensors, Temperature sensors, Process Monitor Ring Oscillator (PMRO), and eFuse.

About the job

In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.

Google’s data centers are the most advanced in the world. In this role you will help build System on a Chips (SoC) that power these data centers by developing and deploying comprehensive test solutions with Automatic Test Equipment (ATE) for New Product Introduction (NPI) and High Volume Manufacturing (HVM) at wafer fabs and Outsourced Assembly and Tests (OSAT). This is an opportunity to create silicon and follow it into the field to close the loop back to design and test for the next generations of chips.

Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.

The US base salary range for this full-time position is $150,000-$223,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target salaries for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google.

Responsibilities

• Participate in ATE test program development for High Volume Manufacturing and Characterization, work with ATE Vendors and internal cross-functional teams.
• Own IP-level test development for Design for testing (DFT) structural tests, functional tests, or eFuse programming.
• Support Chip-level DFT test development for Automatic Test Pattern Generation (ATPG) Scan, Memory Built-In Self Test (MBIST), logic and memory diagnostics, logic redundancy analysis, or memory repair.
• Participate in developing and executing strategies for SoC Product NPI, bring-up, verification, characterization, and qualification support, including bench test, troubleshooting, test coverage optimization, new product Defective Parts per Million (DPPM) correlation, and product correlation between system and ATE.
• Back-stop support for production, including test program upgrade and release, volume data analytics, test time reduction and yield improvement, and
  Return Materials/Merchandise Authorization (RMA) analysis.