Silicon SoC RTL Design/Integration Engineer, Google Cloud

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience
  
• 1 year of experience in ASIC development with Verilog/SystemVerilog, VHDL, or Chisel
  
• Experience in networking, including working with Ethernet, TCP/IP, buffering, queueing, and scheduling
  
• Experience in ASIC design verification, synthesis, timing/power analysis, and Design for Testing (DFT)
  

Preferred qualifications:

• Experience with scripting languages (e.g., Python or Perl)
  
• Experience in SoC designs and integration flows
  
• Knowledge of arithmetic units, bus architectures, processor design, accelerators, or memory hierarchies
  
• Knowledge of high performance and low power design techniques
  

About the job

Google's custom-designed machines make up one of the largest and most powerful computing infrastructures in the world. The Hardware Testing Engineering team ensures that this cutting-edge equipment is reliable. In the R&D lab, you design test equipment for prototypes of our machinery and develop the protocols used to scale these tests for the entire global team. Working closely with design engineers, you give input on designs to improve our hardware until you're sure it meets Google's standards of quality and reliability.

Google Engineers develop the next-generation technologies that change how users connect, explore, and interact with information and one another. In this role, you will develop new products, be versatile and passionate to take on new problems as we continue to push technology forward. As a member of the Digital Design team, you'll work on a networking project to craft the architecture for the current and future ASIC projects, and work with the verification and validation teams to ensure proper testing of features. You will work closely with the Google product teams to ensure their goals are met with the microarchitecture designs. You will also work with physical and manufacturing teams to ensure the designs are viable.

Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.

Responsibilities

• Define the microarchitecture of Subsystems or SoCs and work with the team to deliver a quality, schedule compliant design.
  
• Manage the architecture and microarchitecture of current and future generations of ASIC.
  
• Work closely with Physical Design teams to ensure success. Consolidate demands from Verification, Manufacturing and Product teams.
  
• Help drive internal and external users to vet architecture ideas.