Design Verification Engineer, Machine Learning, Silicon
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Minimum qualifications:
- Bachelor's degree in Electrical Engineering or Computer Science or equivalent practical experience.
- 8 years of experience verifying digital logic at RTL using System Verilog for FPGAs and ASICs.
- Experience verifying digital IP and subsystems.
Preferred qualifications:
- Master's degree or PhD in Electrical Engineering or Computer Science, or a related field.
- 6 years of experience in Electrical Engineering or Computer Science.
- Experience creating/using verification components and environments in methodology (VMM, OVM, UVM).
- Experience with image processing, computer vision, or machine learning applications.
- Experience prototyping and debugging systems on Field Programmable Gate Array (FPGA) platforms.
- Experience with performance verification of Application Specific Integrated Circuit (ASIC) components.
About the job
Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
Responsibilities
- Plan the verification of complex digital design blocks by understanding the design specification and interacting with design engineers to identify important verification scenarios.
- Create and enhance constrained random verification environments using SystemVerilog and UVM, or formally verify designs with Stored Value Account (SVA) and industry leading formal tools.
- Identify and write all types of coverage measures for stimulus and corner cases.
- Debug tests with design engineers to deliver correct design blocks.
- Close coverage measures to identify verification holes and to show progress towards tape out.
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Google is proud to be an equal opportunity and affirmative action employer. We are committed to building a workforce that is representative of the users we serve, creating a culture of belonging, and providing an equal employment opportunity regardless of race, creed, color, religion, gender, sexual orientation, gender identity/expression, national origin, disability, age, genetic information, veteran status, marital status, pregnancy or related condition (including breastfeeding), expecting or parents-to-be, criminal histories consistent with legal requirements, or any other basis protected by law. See also Google's EEO Policy, Know your rights: workplace discrimination is illegal, Belonging at Google, and How we hire.
If you have a need that requires accommodation, please let us know by completing our Accommodations for Applicants form.
Google is a global company and, in order to facilitate efficient collaboration and communication globally, English proficiency is a requirement for all roles unless stated otherwise in the job posting.
To all recruitment agencies: Google does not accept agency resumes. Please do not forward resumes to our jobs alias, Google employees, or any other organization location. Google is not responsible for any fees related to unsolicited resumes.
This job is no longer accepting applications
See open jobs at Google.See open jobs similar to "Design Verification Engineer, Machine Learning, Silicon" Out for Undergrad.