Design Verification Engineer II
Microsoft
Design Verification Engineer II
Raleigh, North Carolina, United States
Save
Overview
Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and deliver trusted experience to customers and partners worldwide and we are looking for engineers to help achieve that mission.
As Microsoft's cloud business grows the ability to deploy new offerings and hardware infrastructure on time, in high volume with high quality and lowest cost is of paramount importance. To achieve this goal, the SCHIE team is instrumental in defining and delivering operational measures of success for hardware manufacturing, improving the planning process, quality, delivery, scale and sustainability related to Microsoft cloud hardware. We are looking for a Design Verification Engineer II who are focused on customer solutions, with insight and industry knowledge to envision and implement future technical solutions that will manage and optimize the Cloud infrastructure.
We are looking for a Design Verification Engineer II to join the team.
Microsoft’s mission is to empower every person and every organization on the planet to achieve more. As employees we come together with a growth mindset, innovate to empower others, and collaborate to realize our shared goals. Each day we build on our values of respect, integrity, and accountability to create a culture of inclusion where everyone can thrive at work and beyond.
In alignment with our Microsoft values, we are committed to cultivating an inclusive work environment for all employees to positively impact our culture every day.
Qualifications
Required Qualifications:
- 5+ years of related technical engineering experience
- OR Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 2+ years technical engineering experience or internship experience
- OR Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience or internship experience.
- 3+ years of pre-silicon System on Chip (SOC), chip level, subsystem or IP verification experience.
- 3+ years of experience with verification principles, object-oriented programming, test plan development, testbench creation, stimulus generation, UVM/Open Verification Methodology (OVM), and coverage-based verification.
- 3+ years of experience in SystemVerilog, C/C++, and scripting languages such as Python, Ruby or Perl.
Other Requirements:
Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.
Preferred Qualifications:
• Demonstrated experience on one or more of the following: Coherency, Caches, Fabrics, Double Data Rate (DDR) controllers, Peripheral Component Interconnect Express (PCIe), Compute Express Link (CXL), Advanced eXtensible Interface(AXI)/Coherent Hub Interface(CHI) protocol bridges or other complex IP/blocks or subsystems.
• Experience with a full product cycle from definition to silicon, including writing IP/block or subsystem level test plans, developing tests, debugging failures and coverage signoff.
• Experience creating, maintaining, or integrating test benches, checkers and stimulus using System Verilog Test Bench (SVTB), Universal Verification Methodology (UVM), Formal Verification and/or C/C++.
• Experience in automating verification processes using Python or another scripting language.
Silicon Engineering IC3 - The typical base pay range for this role across the U.S. is USD $98,300 - $193,200 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $127,200 - $208,800 per year.
Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here: https://careers.microsoft.com/us/en/us-corporate-pay
Microsoft will accept applications for the role until December 27, 2024.
#azurehwjobs #SCHIE
Responsibilities
- Establish yourself as an integral member of a pre-silicon verification and post-silicon validation team for the development of custom silicon components.
- Work with a team to write constrained random stimulus, scoreboards and checkers, and assertions to verify design correctness.
- Develop Verification Intellectual Property (VIP) components to verify home grown designs.
- Develop Universal Verification Methodology (UVM) components to interface between test code and verification simulation environments.
- Define and implement functional coverage and drive coverage closure.
- Collaborate with Architecture, Design, Firmware/Software, Product Engineering, Program Management and third-party vendor teams to ensure pre-and-post-Si testing is comprehensive.
- Develop scripts for verification and validation infrastructure.
- Other