We are seeking a Physical Design Engineer. As part of our DPU silicon team, you will help lead the way for our cutting-edge ASICs, supporting our world-class silicon Physical Design team. In this role, you will tackle key design challenges and support the team with your strong expertise in design flows, automation, and as an interface to our CAD vendors and support teams. You will bring your experience in end-to-end RTL to GDS flows to help drive efficient, on-time execution of our tapeouts.

• Take full ownership of key deigns and deliver for tapeout, meeting all timing, physical, electrical, and manufacturing requirements
• Ownership of flows and automation for key physical design tools (place & route, extraction/STA, physical verification, etc); deploy and test new flows; debug issues & improve existing flows
• Work closely with PD and FE team members across functions and geographies to monitor, track, and resolve issues in our tools and design flows
• Work with tool vendors to resolve key design challenges, improve our flows, and resolve tool issues
• Work closely with PD team members to drive quality and QOR improvements

Required qualifications:

• Bachelor’s degree in computer engineering, electrical engineering, or related field
• 7+ years of physical design experience, with demonstrated experience in delivering tapeout-ready GDS
• 3+ years of experience supporting design flows for synthesis, place-and-route, and signoff
• Deep understanding of Synopsys design tools (e.g., DC, ICC2/Fusion-Compiler, PrimeTime), including integration of in-design signoff flows such as ICV, PrimeClosure, or Redhawk
• Solid scripting skills in Perl or TCL

Preferred qualifications:

• 10+ years of hands-on physical design experience (including synthesis, place & route, LEC, STA, physical verification, and EM/IR closure)
• Deep understanding of Synopsys design tools (e.g., DC, ICC2/Fusion-Compiler, PrimeTime), including integration of in-design signoff flows such as ICV, PrimeClosure, or Redhawk
• Experience with flow automation
• Thorough understanding of STA & timing constraints
• Demonstrated tapeout experience in TSMC 5nm/3nm or below

Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.

This position will be open for a minimum of 5 days, with applications accepted on an ongoing basis until the position is filled.

Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance with religious accommodations and/or a reasonable accommodation due to a disability during the application process, read more about requesting accommodations.