Senior Physical Design Engineer
Microsoft
Responsibilities
- Drive full‑chip physical verification integration, including roll‑ups, hierarchical checks, and signoff collateral generation.
- Perform LVS, DRC, ERC, Antenna, density, and reliability rule checks across block, subsystem, and top level.
- Coordinate with CAD, RTL/Design teams/DFT, Architecture team, Foundry interface team, Technology team & other internal/external partners as essential.
- Help influence design tools, flows, and methodologies in construction and signoff through a data-driven approach.
- Contribute to floor-planning, power grid and design planning activities for correct by construction integration.
- Drive physical verification signoff for tape out across multiple advanced technology nodes.
- Foster collaboration across teams to deliver the best possible solutions, aligned with a One Microsoft mindset.
- Demonstrate technical expertise across various domains of Physical Design Verification.
- Clear communications on project status & planning.
- Demonstrate Microsoft core values: Customer Focus, Adaptability, Collaboration, Growth Mindset, Drive for Results, Influence for Impact, Judgement, and Diversity & Inclusion.
Qualifications
Required Qualifications:
- Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience OR equivalent experience.
Other Requirements:
Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.
- BS/MS in Electrical or Computer Engineering or any related degree.
- 8+ years of experience in semiconductor design.
- Effective communication, collaboration and teamwork skills and ability to contribute to diverse and inclusive teams.
- Experience in Physical Design domain implementing designs through synthesis, floorplanning, place and route, extraction, timing, and physical verification.
- Experience in hierarchical design work, Design Planning and integration with multiple production tape-outs using advanced foundry process nodes.
- Demonstrate technical expertise in all aspects of Physical Design Verification including but not limited to DRC, LVS, Antenna analysis, PERC, ERC and ESD analysis.
- Own complete physical verification and sign off of Critical blocks/Partitions/Sub-systems/Sub-chips instantiating/integrating multiple other Physical partitions. Be fully hands-on in your individual ownerships as individual contributor and collaborate cross-team as required.
- Proficient in integration activities and methodology with hands-on experience.
- Working understanding of PERC and ESD analysis, RDL implementation and bump planning.
- Knowledge of RTL to GDS implementation in Physical Design domain.
- Hands-on experience with performing LVS, DRC, ERC, Antenna, density, and reliability rule checks across block, subsystem, and top level.
- Partner closely with PD flow/CAD team and PD methodology team to flag & fix PD TFM issues upfront and ensure those are fixed in the next PD TFM release from CAD or are updated in the design project layer (as appropriate).
- Skilled in industry-standard EDA tools for physical verification (Calibre or ICV) and working knowledge of tools like Fusion or Innovus for place and route implementation.
- Mentor junior engineers on technical aspects.
- Advanced proficiency in Engineering Change Order (ECO) implementation for layout convergence, with solid knowledge of physical design ECO closure methodologies.
- Demonstrated ownership of deliverables and strong cross-functional teamwork.
- Experience in mentoring, influencing teams, and driving alignment through clear and effective communication.
- Good analytical and problem-solving skills, complemented by advanced scripting capabilities in Perl, TCL, and Python.
Silicon Engineering IC4 - The typical base pay range for this role across the U.S. is USD $119,800 - $234,700 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $158,400 - $258,000 per year.
Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here:
https://careers.microsoft.com/us/en/us-corporate-pay
This position will be open for a minimum of 5 days, with applications accepted on an ongoing basis until the position is filled.
Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance with religious accommodations and/or a reasonable accommodation due to a disability during the application process, read more about requesting accommodations.